1. Field of the Invention
This invention relates to a fabricating method of dual damascene, and more particularly, to a fabricating method of dual damascene that uses low-permissivity dielectric as material.
2. Description of Related Art
The cross-sectional views showing the fabrication process of a conventional fabricating method of dual damascene is shown in FIGS. 1A through 1D. As shown in FIG. 1A, in the fabrication process of a conventional fabricating method of dual damascene, a patterned conducting layer 102 is first formed on a substrate 100, wherein the substrate 100 already contains formed devices (not shown). Then, a oxide layer 104 and a silicon nitride layer 106 are formed on the substrate 100 in sequence. Referring to FIG. 1B, the silicon nitride layer 106 is patterned to form an opening followed by forming an insulating layer 108 over the substrate 100. An anisotropic dry etching process is performed to pattern the insulating layer 108 by using a photoresist layer whereon (not shown). In the meantime, a portion of the oxide layer 104 that is not covered by the patterned silicon nitride layer 106a is also stripped by the anisotropic dry etching process to expose the conducting layer 102. A trench 110b is then formed in insulating layer 108a, and a hole 110a is formed within patterned oxide layer 104a and insulating layer 108a, as shown in FIG. 1C. Referring to FIG. 1D, a barrier layer 112 is deposited on the substrate 100 first, and then, a metal layer 114 is deposited to fill the hole 110a and trench 110b. The metal layer 114 on the insulating layer 108a is removed by a chemical mechanical polishing process to form a via 114a, and conducting lines 114b and 114c in the hole 110a and trench 110b.
Since the design rule of semiconductor devices gradually evolves toward the fabrication process of 0.25 .mu.m, the widths of the via 114a, conducting lines 114b and 114c become accordingly narrower. The distance between conducting lines 114b and 114c is shortened as well. Therefore, the conducting lines 114b and 114c, and the insulating layer 108a between the conducting lines 114b and 114c behave like a capacitor which generates a undesired current, wherein the current disturbs the functions of the conducting lines 114b and 114c, and further causes RC delay that suppresses the efficiency of the device.
Moreover, in the step of forming the barrier layer 112, a downsized opening 110a worsens the step coverage of the barrier layer 112, as shown in FIG. 2. The protuberances of the barrier layer 112 further increase the difficulty on the follow-up deposition process.